COEN6741 (Winter 2018) - Project

The idea of this project is to design a simple pipelined processor, Mini-MIPS, which is a subset of the 32-bit MIPS architecture as described in the textbook (Appendix A). Mini-MIPS uses the same 3 instruction formats of MIPS (R, I and J-types) to implement following 10 instructions:  AND, SUB, XOR, ANDI, SUBI, ADD, BEQ, LW, SW, and JR. It will be assumed that the memory can be accessed in one clock cycle and works synchronously with the CPU (i.e., no need to provide explicit external memory control).

You should proceed step by step towards building the CPU by:

  1. Understanding and analyzing the behavior of each instruction
  2. Defining the detailed micro-operations and encoding of each instruction
  3. Identifying which operations will be parallelized to obtain the pipelined CPU
  4. Designing a detailed block diagram of the CPU
  5. Partitioning the blocks into Datapath and Control Unit
  6. Designing each of the blocks of the Datapath at the RT- level (no need to go at the gate level)
  7. Designing the Control Unit including: decoding, datapath control, pipeline control, etc. (you may leave the control design at the FSM level)
  8. Putting all blocks together to get the full CPU
  9. Simulate your CPU with one test assembly program
You should write a detailed project report documenting above tasks and give a presentation at the end of the term illustrating the main challenges you faced in this project (Please check this ENCS Lab Report Guide).

Special attention should be given to the pipelined design. Your design should be structural hazards free. Data hazards and control hazards should be solved with hardware stalling.

Starting from a paper-and-pencil design of the major blocks, it is suggested you implement your CPU using VHDL or Verilog (e.g. using Modelsim).

The projects can be carried out in any of the general purpose PC labs in the EV building and in AITS labs on the 8th and 9th floors of the Hall building (e.g., H811, H915, H913). However, the PCs must be booted in Linux since all the project tools are installed under Linux and not Windows. In order to access the Hall building laboratories, check on this web site for the door codes

Those that would like to learn about VHDL can acquire this book:
"It's Only VHDL (But I Like It)" by Tadeusz S. Obuchowicz, Pearson Custom Publishing (ISBN: 0-536-75112-9). You may also try this tutorial on VHDL Simulation with Modelsim.

To get started on our Linux environment read these notes. There you find a Verilog-XL tutorial, a fast start, and a detailed reference manual on Verilog. If students wish to synthesize their project, it is possible to run the Mentor Precision RTL syntheis tools f rom the Linux server: computation.encs.concordia.ca by using the command: ssh -Y computation.encs.concordia.ca and following the steps in Part II of VHDL Simulation with Modelsim tutorial. There is also a Verilog on-line documentation on our Linux system (invoke cdsdoc from a Linux command prompt. Within the Verilog-XL turbo folder, there will be two user guides from Cadence). Finally, if you are not sure if you should use VHDL or Verilog, you may read this note from Ted which may or may not give you a clear answer!

References:
1. "Computer Organization and Design: The Hardware/Software Interface" (5th Ed.) by David A. Patterson and John L. Hennessy, Morgan Kauffman Publishers, 2013. ISBN: 978-0124077263.
2. "MIPS Assembly Language Programming", by Robert L. Britton, Pearson Prentice Hall, 2004. ISBN: 978-0131420441.

It is suggested that you work this project in groups of 4 students. The load should be distributed among members of the group, e.g. architecture design, RTL design, control, datapath, pipeline handling, VHDL/Verilog coding, CAD implementation, simulation, report writing, poster design, presentation, etc. Each group has to identify a group leader who will be the contact person with me/TA. A list of all groups will be posted here.

Last but not least. Each group is required to fill the Report Confirmation of Originalty form.

Schedule


Technical Support:

For questions related to the project itself, please contact


For questions related to the VLSI CAD tools, please contact