VLSI CAD Tools
The VLSI Research laboratory is located in Room EV16.173 and EV16.177. The lab is equipped with the following hardware:
University Owned Equipment used for VLSI Research (H964)
1 Sun Enterprise 3500 6 CPU compute server (flash)
7 Sun Ultra 10 workstation with 256 MB memory (jagger,richards,roger,telecaster,
stratocaster, vlsi, entwistle)
1 Sun Sparc 20 with 256 MB memory (luna)
1 Sun sparc 5 with 256 MB memory (rolling)
2 Sun Sparc 5 with 64 MB memory (venus, pluto)
1 Sun Sparc 5 with 32 MB memory (mcewen)
2 NCD X terminals (pink, floyd)
1 HP Plotter 7580B
1 HP LaserJet 4000 TN printer
1 HP ColorLaserJET 4500DN printer
Xilinx FPGA Development boards populated with XCV300 devices.
CMC Loaned Equipment used for VLSI Research
1 Sun Ultra 10 with 512 MB memory and color monitor (jumping)
1 Sun Ultra 10 with 1 GB memory and color monitor (jack)
1 Sun SunBlade 1000 with a 900 MHz CPU, 5 GB memory and 21" color monitor (townshend)
1 Sun UltraSCSI hard drive
1 Sun Enterprise-1 140 with 128 MB memory (vlsi)
1 Sun Disk Multipack 16.8 GB
1 Sun StorEDGE A1000 Disk Array 200 GB
1 Sun Tape Drive EXB 8 mm 5.0 GB
1 Sun CD-ROM drive.
1 IMS XL60 Logic Master Test System
1 TH1000 Mixed Signal IC Test Head
1 Rapid Prototyping board Mod 2
CAD Software
The VLSI research lab is equipped with the following CAD software:
1.Synopsys synthesis and simulation tools.
The Synopsys University Program makes available the following software packages:
Formality
PrimeTime
DC Ultra
Design Analyzer
Library Compiler
Module Compiler
Power Compiler
VHDL Compiler
FPGA Compiler II
VCS (XPF)
DFT Compiler
DesignWare
DesignWare Developer
Behavioral Compiler
2. IC Design and Simulation tools from Cadence Design Systems Inc.
The following software packages are made available through the Cadence University Program:
IC: the Design Framework II environment including Analog Artist, Schematic and Layout editors, circuit extraction, Hspice simulation, DRC, GDSII stream import/export, etc.
DSMSE: Cadence's Silicon Ensemble tool for deep-submicron digital design,place and route.
DSMDP: Cadence's Physical Design Planner tool to perform floorplanning, prior to place and route with Silicon Ensemble.
ICC: Cadence's IC Craftsman. There is no tutorial from CMC regarding this new tool yet.
LDV: Verilog-XL simulator.
SPW: Cadence's Signal Processing Worksystem.
AWB: Analog Workbench from Cadence Design Systems. (NOT AVAILABLE)
FormalCheck: A tool used to perform formal verification of digital circuits.
3. FPGA Implementation tools from Xilinx Inc.
Xilinx Inc. provides the Alliance suite of Field-Programmable Gate Array implementation tools as part of its University Program.
4. Calibre from Mentor Graphics Inc.
The Calibre tool from Mentor Graphics is used to perform design rule checking prior to submitting a design for fabrication to CMC (Canadian Microelectronics Corporation). CMC recommends the use of Caliber to perform design rule checks on large designs.
5. AnisE from Intellisense Corporation. (NO LONGER SUPPORTED !!!!!! Nov. 25, 2004)
AnisE is a powerful, easy to use anisotropic etch process simulation tool for the design of MicroElectromechanical and other microscale devices. The software allows for a designer to layout a microstructure, view a three-dimensional representation of it, access information about the etch rates of different etchants and automatically simulate the etching under different time, temperature,and concentration parameters. The AnisE software includes:
- single and double sided masking
- an empirical database for KOH and TMAH
- etch simulation for a variety of etchant temparatures
- etch simulation for a variety of etchant concentrations
- 2D visualization as the etching proceeds
- 3D visualization of the final etched structure (reproduced directly from the AnisE User Manual UNIX
- Version Documentation
PLEASE NOTE THAT AnisE is NO LONGER SUPPORTED!!!! Our license expired Sept. 15, 2002
and Dr. Landsberger has decided to NOT renew the license.
6. The Virtual Wafer Fab (VWF) Framework from Silvaco International
The VWF is comprised of three basic component sets:
6.1. The Core Tools - these tools simulate either a semiconductor device being processed or a semiconductor device being tested electrically. The Core Tools are ATHENA, ATLAS, and SSUPREM3.
6.2. The VWF Interactive Tools - these tools are designed to be used interactively in the construction of a single input deck. GUI based, they make the job of constructing an input deck more efficient.
6.3. The VWF Automation Tools - these tools enable a user to perform large scale experimental studies to create results for subsequent statistical analysis. (this information reproduced from the VWF Interactive Tools User's Manual Volume 1).
PLEASE NOTE THAT Silvaco is NO LONGER SUPPORTED!!!! Our license expired since Jan. 15, 2007.
7. HSPICE (Simulation Program Integrated Circuit Emphasis)
HSPICE is an optimizing analog circuit simulator used for the simulation of electrical circuits in steady-state, transient, and frequency domains. Circuits can be accurately simulated, analyzed, and optimized from DC to microwave frequencies greater than 100 GHZ.
8. Specman Elite from Verisity Inc.
This tool is available to certain members of the HVG research group.
CMC Provided Design Kits:
Some of the above tools are made available to the university by arrangements between the various software vendors and the Canadian Microelectronics Corporation (CMC). In addition to providing these tools, CMC makes avialable a number of design kits which are used together with certain software tools. These kits are:
mitel15
cmosis5 (no longer supported by CMC, but still being used at ECE for teaching purposes)
cmosp35
cmosp25
cmosp18
cmosp13
cmosp8
mumps
These kits are found in the directory
/CMC/kits/kit_name
where kit_name is one of the above (mitel15, cmosis5, cmosp35, etc)
More information regarding a particular kit may be found in the README file residing in the top-level directory of that kit (for example, /CMC/kits/cmosp35/README). New users of a kit should familiarize themselves with the kit's README file before embarking upon any work.
IMPORTANT : Some of the kits are RESTRICTED ACCESS and require that NON-DISCLOSURE AGREEMENTS be signed before access to a kit is granted. Other kits do not require any non-diclosure agreements to be signed, but require that a user's login name be added to certain UNIX groups in order to gain access. In either case, it is imperative that all users of these kits observe the license regulations pertaining to a kit. This information is found in the file /CMC/kits/kit_name/LICENSE. As an example, here is the LICENSE file from /CMC/kits/cmosp35/LICENSE:
NOTICE
CAREFULLY READ THE FOLLOWING LICENSE AGREEMENT, WHICH IS A LEGAL AGREEMENT
BETWEEN YOU AND THE CANADIAN MICROELECTRONICS CORPORATION/SOCIETE
CANADIENNE DE MICRO-ELECTRONIQUE, REGARDING YOUR USE OF THE CMOSP35
TECHNOLOGY WITH PHANTOM LIBRARIES LICENSED MATERIAL. ACCESS TO THIS LICENSED
MATERIAL IS RESTRICTED TO:
1) UNIVERSITIES WHICH HAVE EXECUTED A CANADIAN UNIVERSITY TSMC LIBRARY
USAGE AGREEMENT, AND
EITHER
2A) UNIVERSITIES WHICH HAVE EXECUTED A TECHNOLOGY USAGE AGREEMENT WITH CANADIAN MICROELECTRONICS CORPORATION/SOCIETE CANADIENNE DE MICRO-ELECTRONIQUE
OR
2B) PERSONS WHO HAVE EXECUTED A CONFIDENTIAL DISCLOSURE AGREEMENT (MUTUAL EXCHANGE) WITH THE CANADIAN MICROELECTRONICS CORPORATION WHICH SPECIFICALLY ADDRESSES THE INTELLECTUAL PROPERTY OF THE TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY (TSMC).
GRANT OF LICENSE
Conditional upon execution of a CANADIAN UNIVERSITY TSMC LIBRARY USAGE
AGREEMENT and either a TECHNOLOGY USAGE AGREEMENT between your university and
the Canadian Microelectronics Corporation/Societe Canadienne de Micro-Electronique,
herein referred to as CMC or a CONFIDENTIAL DISCLOSURE AGREEMENT WHICH SPECIFICALLY
ADDRESSES THE INTELLECTUAL PROPERTY OF THE TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
(TSMC) between you and Canadian Microelectronics Corporation/Societe Canadienne de
Micro-Electronique, herein referred to as CMC, CMC grants to you a LICENSE to use this
LICENSED MATERIAL subject to the terms that follow. Your acceptance or use of the
LICENSED MATERIAL shall constitute your acceptance of such terms.
The LICENSED MATERIAL is confidential, proprietary and is protected by
copyright. You are granted a license to use this material for non-
commercial purposes only. You may use the material for scholarship,
research and teaching purposes. You may not disclose, sell, copy,
distribute, export, publish, circulate or commercially exploit the
LICENSED MATERIAL or any portion thereof without the written consent of
CMC. You may publish results of research using TSMC technology, and you
are required to acknowlege TSMC and CMC in any such publication. You may
NOT publish any information involving or relating directly to the TSMC
manufacturing process without the prior written approval of TSMC and CMC.
All written data delivered to you shall be and remain the property of the
party who furnished it. This data is considered LICENSED MATERIAL under
the terms of this agreement, and as such is subject to the conditions for
LICENSED MATERIAL described above. All such written data shall be
promptly returned to the furnishing party upon written request or
destroyed at the furnishing party's option.
CMC does not represent or warrant that the LICENSED MATERIAL will (1) meet
the Licensee's requirements, (2) operate in a continuous or error free
manner, (3) operate in all the combinations which may be selected for use
by the Licensee. OTHER THAN AS EXPRESSLY SET OUT HEREIN THERE ARE NO
REPRESENTATIONS, WARRANTIES OR CONDITIONS OF ANY KIND WHATSOEVER, EXPRESS
OR IMPLIED, STATUTORY OR ARISING OTHERWISE IN LAW, INCLUDING BUT NOT
LIMITED TO MERCHANTABLE QUALITY AND FITNESS FOR A PARTICULAR PURPOSE IN
CONNECTION WITH THE LICENSED MATERIAL OR USE THEREOF.
Owners of the LICENSED MATERIAL, their affiliates, and CMC are not liable
to each other with respect to claims, expenses and/or judgements. If a
claim is made, CMC and its Member Universities and External Licensees will
immediately discontinue all use of the LICENSED MATERIAL or components
thereof.
This agreement may not be modified except in writing. If any provision is
invalid or unenforceable under applicable law, it shall to that extent be
deemed omitted and the remaining provisions shall continue in full force
and effect. This Agreement shall be construed and enforceable in
accordance with the laws of the Province of Ontario.
The following is a summary of the access to each kit:
cmosis5: no NDA required, no UNIX group permission needed.
cmosp35, cmosp25, cmosp18: no NDA required, login name must be added to the cmosp35 UNIX group, cmosp25 group, or cmosp18 group respectively.
cmosp13: NDA REQUIRED, login name added to the cmosp13 group once NDA has been processed.
The appropriate Non-Disclosure Agreement document may be obtained from the office of the VLSI/CAD Specialist, Mr. Ted Obuchowicz (H964-2).
How to run the tools:
Prior to running a particular tool, one must perform some preliminary work to set up one's UNIX environment properly. The instructions to run a particular tool are found in the directory
/CMC/ENVIRONMENT
Please refer to the appropriate README file in this directory and read the contents. The following are links to the various readme files:
Cadence Tools: README_CADENCE
SPW: README_SPW
Formalcheck: README_FORMALCHECK
Verilog Simulation: README_VERILOG
Caliber: README_CALIBRE
Intellisense Tools: README_INTELLICAD
Silvaco Tools: README_SILVACO
Specman Elite: README_SPECMAN
